1. Field of the Invention
The present invention relates to an active matrix liquid crystal display (AMLCD) having a thin film transistor (TFT) and a pixel electrode connected with the TFT and arranged in a matrix pattern, and a method manufacturing the same, and more particularly, the present invention relates to a method of manufacturing an active panel of the AMLCD for simplifying the manufacturing process and reducing defects in the active panel.
2. Description of the Related Art
Among various display devices displaying picture images on a screen, thin film type flat panel display devices are widely used because they are relatively thin and light weight. Liquid crystal displays are actively being developed and studied because the LCDs provide a sufficiently high resolution and a sufficiently fast response time to display a motion picture.
The principle of the LCD uses optical anisotrophy and polarization properties of liquid crystal materials. The liquid crystal molecules are relatively thin and long and have orientation and polarization properties. Using these properties, the orientation in which the liquid crystal molecules are arranged can be controlled by applying an external electric field. Depending on the orientation of the liquid crystal molecules, light is allowed to either pass through the liquid crystal or is prevented from passing through the liquid crystal. A liquid crystal display effectively uses this characteristic behavior of liquid crystal.
Recently, AMLCDs which include TFTs and pixel electrodes arranged in a matrix pattern have received much attention because they provide enhanced picture quality and natural colors.
The structure of a conventional liquid crystal display is described below. The conventional liquid crystal display includes two panels each having many elements disposed thereon, and a liquid crystal layer formed between the two panels. The first panel or color filter panel located at a first side of the conventional liquid crystal display includes red (R), green (G), and blue (B) color filters sequentially arranged to correspond with an array of pixels disposed on a transparent substrate of the first panel. Between these color filters, a black matrix is arranged in a lattice pattern. A common electrode is formed and disposed on the color filters.
On the other side or second side of the conventional liquid crystal display, the second panel or active panel includes a plurality of pixel electrodes which are located at positions corresponding to positions of pixels and are disposed on a transparent substrate. A plurality of signal bus lines are arranged to extend in a horizontal direction of the pixel electrodes whereas a plurality of data bus lines are arranged in the vertical direction of the pixel electrodes. At a corner of the pixel electrode, a thin film transistor is formed to apply an electric signal to the pixel. The gate electrode of the thin film transistor is connected to a corresponding one of the signal bus lines (or gate bus lines), and the source electrode of the thin film transistor is connected to a corresponding one of the data bus lines (or source bus lines). The end portions of the gate and source bus lines include terminals or pads for receiving signals applied externally thereto.
The above described first and second panels are bonded together and arranged to face each other while being spaced apart by a predetermined distance (known as a cell gap) and a liquid crystal material is injected between the two panels into the cell gap.
The manufacturing process for the conventional liquid crystal panel is rather complicated and requires many different manufacturing steps. More particularly, the active panel having TFTs and pixel electrodes requires many manufacturing steps. Therefore, it is beneficial to reduce the manufacturing steps to reduce the possible defects which may occur during the manufacture of the active panel and to reduce the time, expense and difficulty involved in manufacturing the active panel of the liquid crystal display.
A conventional method of manufacturing an active panel of an AMLCD is described below in terms of a masking process. FIG. 1 is an enlarged plan view of an active panel of an AMLCD and FIGS. 2a-2f are cross-sectional views showing the manufacturing process of the active panel taken along line II--II in FIG. 1.
A first metal is vacuum deposited on a substrate 11 and patterned to form a gate electrode 13, a gate bus line 15 and a gate pad 17, using a first masking process (FIG. 2a).
An insulating material 19a such as silicone nitride and silicone oxide, an intrinsic semiconducting material 21a, an impurity doped semiconducting material 23a and a second metal are preferably sequentially vacuum deposited on the substrate including the first metal, and the second metal is patterned to form a source electrode 33, a drain electrode 43, a source bus line 35 and a source pad 37 using a second masking process (FIG. 2b).
Using the source electrode 33, the drain electrode 43, the source bus line 35 and the source pad 37 as masks, the exposed portion of the impurity doped semiconducting material 23a is removed to form an impure semiconductor layer 23. This is to remove completely the impurity doped semiconducting material 23a located between the source electrode 33 and the drain electrode 43. As a result, an additional mask is not necessary for this process (FIG. 2c).
Next, the insulating material 19a and the intrinsic semiconducting material 21a are simultaneously removed to form a gate insulating layer 19 and a semiconductor layer 21 at an active area located above the gate electrode 13, using a masking process. At this time, the insulating material 19a and the semiconducting material 21a covering the gate bus line 15 and the gate pad 17 are completely removed, whereas the insulating material 19a and the semiconducting material 21a under the source bus line 35 and the source pad 37 remain (FIG. 2d).
An inorganic protection layer 39 is formed on the substrate including the source bus line 33, the drain electrode 43, the gate pad 17 and the source pad 37, by depositing an insulating material such as silicone nitride and silicone oxide. The inorganic protection layer 39 is, then, patterned to form a drain contact hole 61, a gate pad contact hole 63 and a source pad contact hole 65, which expose the drain electrode 43, the gate pad 17 and the source pad 37, respectively, using a fourth masking process (FIG. 2e).
Indium tin oxide is vacuum deposited on the protection layer 39 and, using a fifth masking process, is patterned to form a pixel electrode 53, a gate pad connecting terminal 57 and a source pad connecting terminal 77. The pixel electrode 53 is connected with the drain electrode 43 through the drain contact hole 61, the gate pad connecting terminal 57 is connected with the gate pad 17 through the gate pad contact hole 63 and the source pad connecting terminal 77 is connected with the source pad 37 through the source pad contact hole 65 (FIG. 2f).
Further, additional masking processes may be included, when the gate pad 17 is formed according to a different method or when other elements described as above are to be formed.
In the manufacture of the conventional active panel, there arises a problem of line disconnection during the deposition of indium tin oxide for forming the pixel electrode 53 because of a presence of a stepped profile formed at a location where the pixel electrode 53 and the drain electrode 43 are connected. The stepped profile is formed by the drain electrode 43 extending beyond the edge of the semiconductor layer 21, the doped semiconductor layer 23 and the gate insulating layer 19 (FIGS. 3a, 3b). Undercutting which occurs during the etching processes (FIG. 2d) and is caused by simultaneously etching the semiconducting material 21a, the doped semiconducting material 23a and the gate insulating layer 19, creates the stepped profile. As a result, line disconnection of the pixel electrode 53 occurs at a location marked LD. As a result of this line disconnection of the pixel electrode 53, the production yield of the active panel is reduced.